Kirjasto - Tampereen teknillinen yliopisto

Browsing by Author "Jääskeläinen, Pekka"

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  • A Co-Design Flow for Application-Specific Multicores 
    Jääskeläinen, Pekka; Salminen, Erno; Sanchez de La Lama, Carlos; Takala, Jarmo; Ignacio Martinez, Jose (2011)
    Contemporary embedded systems are often designed as Multiprocessor System-on-Chips (MPSoC) which include multiple processors and other peripherals on a single chip. In contrast to general purpose multiprocessors, the design ...
  • Codesign toolset for application-specific instruction-set processors 
    Jääskeläinen, Pekka; Guzma, Vladimir; Cilio, Andrea; Pitkänen, Teemu; Takala, Jarmo (2007)
    Application-specific programmable processors tailored for the requirements at hand are often at the center of today's embedded systems. Therefore, it is not surprising that considerable effort has been spent on constructing ...
  • Customizable datapath integrated lock unit 
    Jääskeläinen, Pekka; Salminen, Erno; Esko, Otto; Takala, Jarmo (2011)
    Multicore Application-Specific Instruction-Set Processors (MCASIP) offer an interesting alternative for implementing parallel applications in MPSoCs. Flexible MCASIP architecture templates allow matching the instruction ...
  • Customized exposed datapath soft-core design flow with compiler support 
    Esko, Otto; Jääskeläinen, Pekka; Huerta, Pablo; de La Lama, Carlos S.; Takala, Jarmo; Martinez, Jose Ignacio (2010)
    A popular way to exploit high level programming languages in FPGA designs is to use a soft-core with accompanying software development tools. However, a common shortcoming with the current soft-core offerings is their ...
  • Design Methodology for Offloading Software Executions to FPGA 
    Patyk, Tomasz; Salmela, Perttu; Pitkänen, Teemu; Jääskeläinen, Pekka; Takala, Jarmo (2011)
    Field programmable gate array (FPGA) is a flexible solution for offloading part of the computations from a processor. In particular, it can be used to accelerate an execution of a computationally heavy part of the software ...
  • From Parallel Programs to Customized Parallel Processors 
    Jääskeläinen, Pekka (2012-11-08)
    The need for fast time to market of new embedded processor-based designs calls for a rapid design methodology of the included processors. The call for such a methodology is even more emphasized in the context of so called ...
  • Impact of software bypassing on instruction level parallelism and register file traffic 
    Guzma, Vladimir; Jääskeläinen, Pekka; Kellomäki, Pertti; Takala, Jarmo (2008)
    Software bypassing is a technique that allows programmer-controlled direct transfer of results of computations to the operands of data dependent operations, possibly removing the need to store some values in general purpose ...
  • Instruction Set Simulator for Transport Triggered Architectures 
    Jääskeläinen, Pekka (2005-09)
    Due to specific requirements of some of embedded system applications, general purpose processors are usually not the most optimal ones for the task at hand. Thus, there is a need for application-specific processors, which ...
  • Operation set customization in retargetable compilers 
    Kultala, Heikki; Jääskeläinen, Pekka; Takala, Jarmo (2011)
    The core tool in Application-Specific Instruction Set Processor (ASIP) design toolsets is a retargetable compiler, which can generate efficient code to any processor developed with the toolset. Such a compiler must ...
  • Programmable and scalable architecture for graphics processing units 
    Sanchez de la Lama, Carlos; Jääskeläinen, Pekka; Takala, Jarmo (2009)
    Graphics processing is an application area with high level of parallelism at the data level and at the task level. Therefore, graphics processing units (GPU) are often implemented as multiprocessing systems with high ...
  • Reducing context switch overhead with compiler-assisted threading 
    Jääskeläinen, Pekka; Kellomäki, Pertti; Takala, Jarmo; Kultala, Heikki; Lepistö, Mikael (2009)
    Multithreading is an important software modularization technique. However, it can incur substantial overheads, especially in processors where the amount of architecturally visible state is large. We propose an implementation ...
  • Reducing the overheads of hardware acceleration through datapath integration 
    Jääskeläinen, Pekka; Kultala, Heikki; Pitkänen, Teemu; Takala, Jarmo (2008)
    Hardware accelerators are used to speed up execution of specific tasks such as video coding. Often the purpose of hardware acceleration is to be able to use a cheaper or, for example, more energy economical processor for ...
  • Resource conflict detection in simulation of function unit pipelines 
    Jääskeläinen, Pekka; Guzma, Vladimir; Korhonen, Viljami (2008)
    Processor simulators are important parts of processor design toolsets in which they are used to verify and evaluate the properties of the designed processors. While simulating architectures with independent function unit ...