Functional RAM testing

Abstract

In this Thesis is a functional random access memory (RAM) model introduced as well as functional faults which are derived from that model. All possible fault combinations are also examined. Two different methods for functional RAM testing are approached: deterministic testing and random testing. In deterministic testing the input data is known beforehand and in random testing the input data is a string of pseudorandom vectors. The aim of this Master's Thesis was to design a test procedure that could be used for detecting and diagnosing faults in a synchronous DRAM memory (SDRAM) and it's interface in less than two seconds. The memory size was assumed to be 64Mbit.