Higher abstraction level ASIC design methods

Abstract

Modern SoC ASIC circuits are getting more and more complex as the advances in silicon technology allow for the integration of more functions on a single ship. At the same time the short product life spans call for shorter development cycles. One solution to bridging this gap is the entry of the implementable design at a higher abstraction level.- The current VHDL based design flow consists of manually entering the desired fixed architecture implementing the desired functions. This register transfer Level design style means that the memory elements and the dataflow between them are implicitly declared. This abstraction level means that much of the design time must be spent deciding the final architecture instead of the algorithmic behaviour. The good thing about the RTL design flow is the maturity of the design tools involved.- The purpose of this thesis was not to pick the absolute best method but to take a look at the available candidates. Although the move to a higher level will no doubt happen in the future, the methods will need to mature before a choice between them can be made. The support from major EDA vendors and system design houses will certainly play a major role in determining the life span of these products. Also the suitability of the different methods for describing different types of algorithms may lead to the adoption of several of these tools in the design flow. This thesis can be used as a starting point for further evaluation work. /Kir10