Optimizing Algorithms for Task Graph Mapping on Multiprocessor System on Chip

Abstract

The objective of this Thesis is to analyze and improve MPSoC design space exploration, specifically the task mapping using Simulated Annealing (SA) with fully automatic optimization. The work concentrates mostly on application execution time optimization. However, a trade-off between memory buffer and time optimization and a trade-off between power and time optimization is also analyzed. Applications are represented as public Standard Task Graph sets and Kahn Process Networks (KPNs). Main focus is on SA as the optimization algorithm for task mapping. A state of the art survey is presented on using SA for task mapping. Thesis analyzes the impact of SA parameters on convergence. A systematic method is presented for automatically selecting parameters. The method scales up with respect to increasing HW and SW complexity. It is called Simulated Annealing with Automatic Temperature (SA+AT). Optimal subset mapping (OSM) algorithm is presented as a rapidly converging task mapping algorithm. SA+AT is compared with OSM, Group Migration, Random Mapping and a Genetic Algorithm. SA+AT gives the best results. OSM is the most efficient algorithm. Thesis presents new data on the convergence of annealing. Answers are given to global optimum convergence properties and the convergence speed in terms of mapping iterations. This covers optimization of the run-time of mapping algorithms so that a trade-off can be made between solution quality and algorithm's execution time. SA+AT saves up to half the optimization time without significantly decreasing solution quality. Recommendations are presented for using SA in task mapping. The work is intended to help other works to use SA. DCS task mapper, an open source simulator and optimization program, is presented and published to help development and evaluation of mapping algorithms. The data to reproduce Thesis experiments with the program is also published.