A Co-Design Flow for Application-Specific Multicores
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Tiedostot
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URN:
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http://URN.fi/URN:NBN:fi:tty-201201181009
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Nimeke:
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A Co-Design Flow for Application-Specific Multicores |
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Tekijä:
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Jääskeläinen, Pekka; Salminen, Erno; Sanchez de La Lama, Carlos; Takala, Jarmo; Ignacio Martinez, Jose |
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Julkaisun tyyppi:
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Konferenssijulkaisu - Conference paper |
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Julkaisuaika:
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2011 |
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DOI:
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http://dx.doi.org/10.1109/SAMOS.2011.6045448
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Kuvaus:
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© 2011 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. |
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Yliopisto:
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Tampereen teknillinen yliopisto - Tampere University of Technology |
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Tiedekunta:
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Tieto- ja sähkötekniikan tiedekunta – Faculty of Computing and Electrical Engineering |
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Laitos:
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Tietokonetekniikan laitos – Department of Computer Systems |
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Tiivistelmä:
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Contemporary embedded systems are often designed as Multiprocessor System-on-Chips (MPSoC) which include multiple processors and other peripherals on a single chip. In contrast to general purpose multiprocessors, the design of an embedded MPSoC is usually customized to the requirements of the application domain. The need for fast time to market of new embedded MPSoC designs calls for a rapid design flow of the included customized processors.
This paper proposes a Multicore Application-Specific Instruction Set Processor (MCASIP) co-design flow that exploits parallel programming languages as the application description format. The designer can capture the parallelism of the algorithm and exploit specialized instructions using a single high-level programming language. Parallelism of the designed MCASIP architectures can be scaled both at instruction and task levels, enabling easy exploration of the MCASIP design space. This paper describes the design flow and its key technical challenges, and demonstrates its scalability potential. The presented preliminary results show promise for an efficient multiprocessor design methodology. |
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Tekijänoikeudet:
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This publication is copyrighted. You may download, display and print it for Your own personal use. Commercial use is prohibited. |
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