Reconfigurable coarse-grain architecture for multimedia algorithms

Abstract

In this thesis has been developed a coarse-grain reconfigurable coprocessor called Butter. First of all have been made some modifications to its interconnection network, to its configuration memories and to its basic cell. To configure the device have been designed a graphical programming tool using the Java language.Butter was prototyped on a FPGA board and a 2D low-pass image filter was mapped on it.In a second step a new platform containing an entire programmable system based on a 32-bit RISC microprocessor and the reconfigurable coprocessor was developed. A generic convolution 2D image filter was mapped on the coprocessor.Finally has been made an implementation of an H.264 baseline decoder for the system.