| Title: | AD-conversion and digital filtering requirements in flexible receivers |
| Author: | Pirskanen, Juho |
| Abstract: | In mobile communication, a tremendous growth has been experienced during 1990's. A strong trend in the today's mobile communications is to provide global coverage and high capacity for high speed data services in a more flexible way. - The third generation mobile system is being standardized to provide high capacity and global coverage. Because second generation system, like GSM, will not vanish in the near future, a mobile terminal capable of operating in both second and third generation networks would have superior position in the market. - To achieve low cost, small-sized, and more flexible devices, the complexity of the receiver's analog front-end must be reduced as much as possible: An interesting possibility to implement a dual mode receiver for WCDMA and GSM system is a wide-band analog front-end together with wide band AD-conversion. In such a system, the required system characteristics are defined mostly by DSP: For the dual-mode concept, possible receiver architectures are considered. In addition, the selectivity requirements for both receiver branches are derived from the WCDMA channel, where the required IF-filtering is implemented by a highly selective SAW filter. -It is shown how the performance requirements of the analog-to-digital converter and the sample and hold circuit depend on the bandwidth of the receiver's analog front-end. Based on the performance requirements, a special ADC architecture, sigma-delta regulation, is investigated. - In this thesis, the DSP-filtering requirements for both systems are derived. The requirements are calculated for interfering RF-channels after the SAW filter. Based on the noise shaping function of the sigma-delta modulator, DSP-filtering requirements for the dual mode receiver are completed. A complete decimation structure is presented, based on proposed IF frequency and sampling rate. The obtained DSP-filtering requirements are then used to design the first decimation stage. In the first decimation stage, the decimation filtering is done by using theCIC-filter structure. /Kir10 |
| Comment: | TTY:n kirjastossa laadittu tiivistelmä |
| Issue date: | 2000-06-07 |
| URN: | http://URN.fi/URN:NBN:fi:tty-200907105002 |
| Publication type: | Diplomityö |
| Language: | eng |
| Pages: | 84 s |
| Examiner: |
Renfors, Markku Tiilikainen, Mika |
| University: | Tampereen teknillinen korkeakoulu |
| Faculty: | Sähkötekniikan osasto |
| Department: | Tietoliikennetekniikan laitos |
| Degree Programme: |
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