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Abstract:
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The study deals with the FPGA circuits used in the Rosetta spacecraft, more precisely in its power distribution units. Rosetta spacecraft is a probe, which will be sent to investigate the comet Wirtanen. The purpose of this 10,5year long mission is to provide more information about the material of the comet. The rosetta Spacecraft includes power distribution units (PDUs), which are used for distributing electric power for different instruments inside the spacecraft. The PDUs include control logic, which is used for receiving commands from earth and decoding and transmitting these commands to different functional blocks inside a PDU. Control logic also gathers status information and analog voltage and current levels from other boards general special data packets, which are sent back to earth. - This control logic is implemented with Actel's radiation tolerant FPGA-circuits design specially for space applications. There are many different environmental phenomena in space, which may affect the operation of electrical components. For example, highly energetic particles may cause single-event upset (SEU) for micro electronic circuits and total dose radiation can degrade electronic components. A single event upset causes a register bit to change state and this may lead to an error situation inside a dense FPGA-circuit. Radiation tolerant FPGA are designed to withstand high radiation levels and highly energetic particles, which prevents SEU-errors from occurring. - Both PDU include two control boards and each control board has two different FPGA circuits, a Command delivery Circuit (CDC) and a Status Generator Circuit (CGC). The CDC circuit consists of functions used in decoding and transmitting received command to target boards. Functions inside the SGC circuit are used in generating internal clocks, data packets, special commands and control signals for AD-converter and SRAM memory located on control board. FPGAs were designed by using VHDL coding and normal FPGA design flow, which includes architectural and VHDL design, behavioural simulations, logic synthesis, place and routes, timing simulations, and FPGA programming and testing. - One part of the work was to create an extensive test bench, by using VHDL, for behavioural and timing simulations. This test bench modelled other broads and functions of the PDUs and it verified the correct format of different telemetry data packets. Finally, the design errors found while testing the programmed FPGAs are analysed, and some methods are presented in order to prevent similar. /Kir10 |