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Abstract:
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Electrical are widely used in modern technological products. In almost every case it is more than reasonable to assume that the product includes at least one integrated circuit. Due to the number of different applications, a wide range of circuits is needed. Despite of numerous standard circuits and component vendors, some designs require special components that are tailored for this particular application. Designing of these application specific integrated circuits (ASICs) is a very demanding task that challenges capabilities of circuit designer and used designed tools. The rapid development of silicon processing technologies is surely not alleviating designing problems. With new technologies, it is possible to produce circuits that are so thick that the exploitation of circuit's capabilities with current design methods in reasonable time is almost impossible. To overcome these problems, new more efficient designing methods are developed. Currently almost all ASIC designing projects are realized using hardware description languages, like VHDL, and register transfer level (RTL) description. This kind of approaches has two main disadvantages. Firstly, a description of a complex system contains usually a vast number of rows and thus more possibly errors. Secondly, the description itself can become so complex that it might be impossible to comprehend. Especially the latter case is a problem when someone else than the original creator tries to study the description. In order to improve these features, there is at least two possibility solutions. Efficiency of the description can be improved by raising the abstraction level of the description from the RTL to behavioural level. In this level, the designer can determine the system in as algorithms without paying so much attention to the resulting hardware. Due to this, the description contains fewer rows and is more readable. Another way to improve ASIC design flow is to use graphical approach. If the system can be determined without text description using only graphical building blocks, the intelligibility is largely improved. It is quite clear that the structure of a design is much easier to perceive from picture than from several text files.This thesis evaluates two new design methods, one high-level description language (Celoxica's Handel-C) and one graphical description tool (Xilinx's System Generator), against traditional VHDL description. In order to generate graded details, a particular design case (pipelined unified DCT/IDCT system) is mapped into an FPGA chip using each method. Conclusions made in this thesis are base on required FPGA resources, maximum are suitable for FPGA designing and they are good in a certain sector, but as a whole, traditional RTL level description is still the most suitable method for timing and size critical applications. /Kir10 |