The impact of logic style on low power, low voltage digital design

Abstract

Low power consumption is required in portable electronic appliances. Design for low-power demands careful consideration in every level of digital integrated circuit design flow. It is possible to improve the power efficiency even in the physical level of a design. A brief description of MOS transistor physics is presented. The theory of power dissipation in CMOS circuits is shortly summarised. Some future trends are disclosed.The logic styles of this research are presented. There are four logic styles with logic tree structure and seven logic styles with pass-transistor structure. The logic styles are first simulated in schematic test case with HSPICE. Two prominent logic styles, SCMOS and DCVSPG, were selected for low-power operation study in the layout level. Three layout test cases were generated. Net lists were extracted with parasitic data and simulated with PowerMill simulation tool. According to the simulations, SCMOS logic style performs best in terms of power dissipation. It is also robust against process variations, voltage downscaling, and temperature. Accuracy of the simulation results of the results were considered and found sufficient to draw the conclusions mentioned above. /Kir10