Benchmarking COFFEE RISC processor core

Abstract

The thesis describes the benchmarking of the COFFEE RISC processor core by measuring the number of instruction cycles required to execute certain algorithms. Benchmarking takes into account that COFFEE RISC core is intended for general purpose and it is a fixed point processor. The algorithms are programmed in assembly code and then executed on the instruction set simulator. Also some benchmarks in C language are used for evaluating the optimization of compiler against the hand coded assembly. In the analysis, execution cycle count, wait cycle count and statistics about memory traffic are evaluated. Based on the results the aim is to improve hardware by making the common case faster, scheduling instructions better or recommending hardware acceleration or parallel execution with multiple cores. /Kir09