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Kirjasto - Tampereen teknillinen yliopisto

Browsing Research publications by Author "Jääskeläinen, Pekka"

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  • Xianjun, Jiao; Canfeng, Chen; Jääskeläinen, Pekka; Guzma, Vladimír; Berg, Heikki (2013-07-01)
    Parallel implementations of Turbo decoding has been studied extensively. Traditionally, the number of parallel sub-decoders is limited to maintain acceptable code block error rate performance loss caused by the edge effect ...
  • Jääskeläinen, Pekka; Salminen, Erno; Sanchez de La Lama, Carlos; Takala, Jarmo; Ignacio Martinez, Jose (2011)
    Contemporary embedded systems are often designed as Multiprocessor System-on-Chips (MPSoC) which include multiple processors and other peripherals on a single chip. In contrast to general purpose multiprocessors, the design ...
  • Jääskeläinen, Pekka; Guzma, Vladimir; Cilio, Andrea; Pitkänen, Teemu; Takala, Jarmo (2007)
    Application-specific programmable processors tailored for the requirements at hand are often at the center of today's embedded systems. Therefore, it is not surprising that considerable effort has been spent on constructing ...
  • Jääskeläinen, Pekka; Salminen, Erno; Esko, Otto; Takala, Jarmo (2011)
    Multicore Application-Specific Instruction-Set Processors (MCASIP) offer an interesting alternative for implementing parallel applications in MPSoCs. Flexible MCASIP architecture templates allow matching the instruction ...
  • Esko, Otto; Jääskeläinen, Pekka; Huerta, Pablo; de La Lama, Carlos S.; Takala, Jarmo; Martinez, Jose Ignacio (2010)
    A popular way to exploit high level programming languages in FPGA designs is to use a soft-core with accompanying software development tools. However, a common shortcoming with the current soft-core offerings is their ...
  • Patyk, Tomasz; Salmela, Perttu; Pitkänen, Teemu; Jääskeläinen, Pekka; Takala, Jarmo (2011)
    Field programmable gate array (FPGA) is a flexible solution for offloading part of the computations from a processor. In particular, it can be used to accelerate an execution of a computationally heavy part of the software ...
  • Viitanen, Timo; Kultala, Heikki; Jääskeläinen, Pekka; Takala, Jarmo (2012-10-12)
    Most power dissipation in Very Large Instruction Word (VLIW) processors occurs in their large, multi-port register files. Transport Triggered Architecture (TTA) is a VLIW variant whose exposed datapath reduces the need for ...
  • Guzma, Vladimir; Jääskeläinen, Pekka; Kellomäki, Pertti; Takala, Jarmo (2008)
    Software bypassing is a technique that allows programmer-controlled direct transfer of results of computations to the operands of data dependent operations, possibly removing the need to store some values in general purpose ...
  • Viitanen, Timo; Jääskeläinen, Pekka; Takala, Jarmo (2013-10)
    Recent embedded DSPs are incorporating IEEE-compliant floating point arithmetic to ease the development of, e.g., multiple antenna MIMO in software-defined radio. An obvious choice of FPU architecture in DSP is to include ...
  • Kultala, Heikki; Jääskeläinen, Pekka; Takala, Jarmo (2011)
    The core tool in Application-Specific Instruction Set Processor (ASIP) design toolsets is a retargetable compiler, which can generate efficient code to any processor developed with the toolset. Such a compiler must ...
  • Sanchez de la Lama, Carlos; Jääskeläinen, Pekka; Takala, Jarmo (2009)
    Graphics processing is an application area with high level of parallelism at the data level and at the task level. Therefore, graphics processing units (GPU) are often implemented as multiprocessing systems with high ...
  • Jääskeläinen, Pekka; Kellomäki, Pertti; Takala, Jarmo; Kultala, Heikki; Lepistö, Mikael (2009)
    Multithreading is an important software modularization technique. However, it can incur substantial overheads, especially in processors where the amount of architecturally visible state is large. We propose an implementation ...
  • Jääskeläinen, Pekka; Kultala, Heikki; Pitkänen, Teemu; Takala, Jarmo (2008)
    Hardware accelerators are used to speed up execution of specific tasks such as video coding. Often the purpose of hardware acceleration is to be able to use a cheaper or, for example, more energy economical processor for ...
  • Jääskeläinen, Pekka; Guzma, Vladimir; Korhonen, Viljami (2008)
    Processor simulators are important parts of processor design toolsets in which they are used to verify and evaluate the properties of the designed processors. While simulating architectures with independent function unit ...
  • Viitanen, Timo; Jääskeläinen, Pekka; Esko, Otto; Takala, Jarmo (2013)
    Digital Signal Processing (DSP) algorithms on low-power embedded platforms are often implemented using fixed-point arithmetic due to expected power and area savings over floating-point computation. However, recent research ...
  • Helkala, Janne; Viitanen, Timo; Kultala, Heikki; Jääskeläinen, Pekka; Takala, Jarmo; Zetterman, Tommi; Berg, Heikki (2014-07-14)
    The SRAM memories used for embedded micro-processor devices consume a large portion of the system's power. The power dissipation of the instruction memory can be limited by using code compression methods, which may require ...