Design and Implementation of Scalable FFT Processor for Wireless Applications
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In the recent past, communication is predominantly becoming wireless which is a drastic shift from wired communication. Generally, the transmitted radio signal over a wireless channel is subject to more distortion, more interference and more noise than a signal over wired channel. In other words, the SNR of received signal over a wireless channel is comparatively lower compared to received signal over a wired channel. Hence, to recover original data from received signal, wireless communication systems have to be more robust and efficient in recovering original data. Wireless communication systems these days adopt efficient multi-carrier transmission technique such as OFDM in their transceivers. And majority of the commercial wireless standards are OFDM based. OFDM based wireless standards demand highly efficient baseband hardware in communication systems. The baseband hardware needs to meet stringent design parameters such as high speed, low power, low area, low cost, highly fexible and highly scalable. Modern wireless systems support multiple standards to meet the demands of end user application requirements. A wireless system while supporting multiple standards, should also satisfy performance requirements of those supported standards. Wireless transceivers based on SDR platform support multiple wireless standards. Meeting performance requirements of multiple standards is a challenge while designing baseband hardware. To design an efficient OFDM baseband hardware, it is necessary to efficiently design its performance critical component. FFT computation is one of the most performance critical component in an OFDM system. Designing FFT hardware to support multiple wireless standards while meeting the above specified performance requirements is a challenging task. In this thesis work a N-point scalable novel FFT processor architecture was proposed. A radix-2 fixed point 16-bit N-point scalable FFT processor was designed and prototyped using VHDL on an Altera Stratix V FPGA device 5SGSMD5K2F40C2. The processor was implemented targeting SDR platforms supporting multiple OFDM based wireless standards. The processor operates at a maximum frequency of 200MHz and uses less than 1% of hardware resources on the FPGA. It meets the performance requirements of OFDM based wireless standards such as IEEE 802.11a/g, IEEE 802.16e, 3GPP-LTE, DAB and DVB-T. The FFT processor based on proposed novel architecture has a better performance in terms of speed, flexibility and scalability when compared to existing fixed as well as variable length FFT processors.