Design and implementation of a FFT pruning engine for DSA-enabled cognitive radios
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Dynamic spectrum access (DSA) communications are an efficient way to improve the efficiency of spectrum utilization in the context of cognitive radio networks. In fact, through the utilization of DSA-enabled communications, secondary users are able to utilize portions of spectrum that are currently left unused by primary users both in time and space domains. However, the available spectrum is highly scattered throughout the frequencies and therefore agile transmission techniques have to be used to efficiently allocate the secondary user’s communications in the available spectrum gaps. In this context, Non-Contiguous OFDM (NC-OFDM) and Discontinuous-OFDM (D-OFDM) systems are feasible solutions for fully exploit the available spectrum, even if highly scattered. NC-OFDM, as well as D-OFDM, is able to turn on and off its sub-carriers allocations, in order to place the transmitted data in the unused spectrum gaps, without interfering with the communications of primary users. From an architectural point of view, the utilization of NC-OFDM enables to improve the energy efficiency of the (de)modulation block. In fact, the computation of FFT/IFFT can be simplified via the utilization of pruning algorithms. Pruning algorithms are able to eliminate at run-time the computation of dummy operations, such as the addition or the multiplication of zero terms, reducing the complexity of the original algorithm. At receiver side the unused sub-carriers are considered as zero-value inputs in the FFT block. Thus, in a scenario where the number of unused sub-carrier is significant, FFT pruning is able to lighten the computation of the FFT, enabling a more efficient implementation of the algorithm. This research work presents the design and implementation of a FFT pruning block, which is an extension to the FFT core for OFDM demodulation, enabling run-time pruning of the FFT algorithm, without any restrictions on the distribution pattern of the active/inactive sub-carriers. The design and implementation of FFT processor core is not the part of this work. The whole design was prototyped on an ALTERA STRATIX V FPGA to evaluate the performance of the pruning engine. Synthesis and simulation results showed that the logic overhead introduced by the pruning block is limited to a 10% of the total resources utilization. Moreover, in presence of a medium-high scattering of the sub-carriers, power and energy consumption of the FFT core were reduced by a 30% factor.