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dc.creatorHelkala, Janne
dc.date.accessioned2014-05-23T09:24:35Z
dc.date.available2014-05-23T09:24:35Z
dc.date.issued2014-05-23
dc.identifier.urihttp://dspace.cc.tut.fi/dpub/handle/123456789/22219
dc.description.abstractThe Static Random-Access Memory (SRAM) modules used for embedded microprocessor devices consume a large portion of the whole system’s power. The memory module consumes static power on keeping awake and dynamic power on memory accesses. The power dissipation of the instruction memory can be limited by using code compression methods, which reduce the memory size. The compression may require the use of variable length instruction formats in the processor. The power-efficient design of variable length instruction fetch and decode units is challenging for static multiple-issue processors, because such architectures have simple hardware to begin with, as they aim for very low power consumption on embedded platforms. The power saved by using these compression approaches, which necessitate more complex logic, is easily lost on inefficient processor design. This thesis proposes an implementation for instruction template-based compression, its decompression and two instruction fetch design alternatives for variable length instruction encoding on Transport Triggered Architecture (TTA), a static multiple-issue exposed data path architecture. Both of the new fetch and decode units are integrated into the TTA-based Co-design Environment (TCE), which is a toolset for rapid designing and prototyping of processors based on TTA. The hardware description of the fetch units is verified on a register transfer level and benchmarked using the CHStone test suite. Furthermore, the fetch units are synthesized on a 40 nm standard cell Application Specific Integrated Circuit (ASIC) technology library for area, performance and power consumption measurements. The power cost of the variable length instruction support is compared to the power savings from memory reduction, which is evaluated using HP Labs’ CACTI tool. The compression approach reaches an average program size reduction of 44% at best with a set of test programs, and the total power consumption of the system is reduced. The thesis shows that the proposed variable length fetch designs are sufficiently low-power oriented for TTA processors to benefit from the code compression.en
dc.format.extentvii, 62
dc.format.mimetypeapplication/pdf
dc.language.isoenen
dc.rightsThis publication is copyrighted. You may download, display and print it for Your own personal use. Commercial use is prohibited.en
dc.titleVariable Length Instruction Compression on Transport Triggered Architecturesen
dc.title.alternativeSiirtoliipaisuarkkitehtuurin muuttuvanmittaisten käskyjen pakkaus
dc.identifier.urnURN:NBN:fi:tty-201405231224
dc.contributor.laitosTietotekniikan laitos – Department of Pervasive Computingen
dc.contributor.tiedekuntaTieto- ja sähkötekniikan tiedekunta – Faculty of Computing and Electrical Engineeringen
dc.contributor.yliopistoTampereen teknillinen yliopisto - Tampere University of Technologyfi
dc.programmeSignaalinkäsittelyn ja tietoliikennetekniikan koulutusohjelmaen
dc.date.published2014-06-04
dc.contributor.laitoskooditie
dc.contributor.thesisadvisorJääskeläinen, Pekka
dc.contributor.degreesupervisorJääskeläinen, Pekka
dc.contributor.degreesupervisorTakala, Jarmo
dc.type.ontasotDiplomityö - Master's thesis


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