Show simple item record

dc.creatorJärvelä, Mikko
dc.date.accessioned2014-05-26T09:26:08Z
dc.date.available2014-05-26T09:26:08Z
dc.date.issued2014-05-26
dc.identifier.urihttp://dspace.cc.tut.fi/dpub/handle/123456789/22234
dc.description.abstractHigh performance and low power consumption requirements usually restrict the design process of embedded processors. Traditional design solutions do not apply to the requirements today, but instead demands exploiting varying levels of parallelism. In order to reduce design time and effort, a powerful toolset is required to design new parallel processors effectively. TTA-based Co-design Environment (TCE) is a toolset developed in Tampere University of Technology for designing customized parallel processors. It is based on a modular Transport Triggered Architecture (TTA) processor architecture template, which provides easy customization and allows exploiting instruction-level parallelism for high performance execution. Single Instruction, Multiple Data (SIMD) paradigm provides powerful data-level parallel vector computation for many applications in embedded processing. It is one of the most common ways to exploit parallelism in today's processor designs in order to gain greater execution efficiency and, therefore, to meet the performance requirements. This work describes how data-level parallel SIMD support is introduced and integrated to the TCE design flow for more diverse parallelism support. The support allows designers to customize and program processors with wide vector operations. The work presents the required modification points along with the new tools that were added to the toolset. Much weight is given for the retargetable compiler, which must be able to adapt to all resources on TTA machines. The added tools were required to provide as much automatic behavior as possible to maintain effective design flow. In addition, the thesis presents how the modifications and new features were verified.en
dc.format.extentvii, 59
dc.format.mimetypeapplication/pdf
dc.language.isoenen
dc.rightsThis publication is copyrighted. You may download, display and print it for Your own personal use. Commercial use is prohibited.en
dc.titleVector Operation Support for Transport Triggered Architecturesen
dc.identifier.urnURN:NBN:fi:tty-201405261239
dc.contributor.laitosTietotekniikan laitos – Department of Pervasive Computingen
dc.contributor.tiedekuntaTieto- ja sähkötekniikan tiedekunta – Faculty of Computing and Electrical Engineeringen
dc.contributor.yliopistoTampereen teknillinen yliopisto - Tampere University of Technologyfi
dc.programmeSignaalinkäsittelyn ja tietoliikennetekniikan koulutusohjelmaen
dc.date.published2014-06-04
dc.contributor.laitoskooditie
dc.contributor.thesisadvisorJääskeläinen, Pekka
dc.contributor.degreesupervisorTakala, Jarmo
dc.type.ontasotDiplomityö - Master's thesis


Files in this item

Thumbnail

This item appears in the following Collection(s)

Show simple item record