Assessment of data rates on the internal and external CPU interfaces and its applications for Wireless Network-on-Chip development
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Nowadays central processing units (CPUs) are the major part of the personal computers, and usually their progress defines personal computers (PCs) progress. However, modern CPU architecture has a set of limitations mentioned in this thesis. As a result, new CPU architectures are now under development. Most prospective solution in this field are based on a proposed concept of Wireless Networks-on-Chip (WNoCs), where part of wired connections is changed into wireless links. However in order to design and develop this kind of system, information about data rates on the internal and external CPU interfaces of modern CPUs is needed. Main goals set in the beginning of working on this thesis were to get this data rates assessment and give an assessment of suitable wireless technologies for milticore CPUs with different number of cores. In this thesis CPU evolution is described and peculiarities of modern CPU architectures are mentioned. Besides state-of-the-art overview for Wireless Networks-on-Chip is provided. Moreover, full methodology of measuring intra-CPU counters and getting data rates on cache bus between second and third level caches and third level cache and random access memory (RAM) controller bus are provided. Dependencies of data rates on interfaces of interest on the number of active CPU cores and CPU clock frequency are studied and provided in a form of plots. Also differences in the traffic for different types of CPU load are provided as bar diagrams. For testing we used several real-life tasks that are typical for CPUs and artificial tests which are represented as programs written in C programming language. In addition, extrapolation model for CPUs with bigger amount of cores is provided and assumption about suitable wireless technologies for different number of CPU cores is made.