Assertion-based Formal Verification of a SoC Module Software Interface
Mäki-Äijö, Santeri Jaakko
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Väitelausekkeisiin pohjautuva järjestelmäpiirimoduulien ohjelmistorajapintojen muodollinen varmennus
The goal of this thesis was to develop a new assertion-based formal verification method to verify SoC module SW interfaces used at Nokia Mobile Networks SoC R&D. Currently used simulation-based methods had been found to be ineffective in finding all bugs in SW interfaces. Therefore, a new method was needed to replace or support the current one. Previous studies had been made about the assertion-based formal verification method on different kinds of designs. The results implied that there is also potential to apply the method for SW interface verification. In this thesis, the suitability of the method for this task was examined in practice. To use the method, SystemVerilog assertions verifying the whole functionality of the SW interface had to be created first. The creation of assertions was carried out in two phases. In the first phase, the goal was to create assertions that could verify the SW interface functionality. The goal was achieved by utilizing the assertions created manually and by a formal verification tool. However, the coverage of SW interface functionality and code achieved with the assertions was not good enough. Thus, the assertions had to be improved. In the second phase, phase 1 assertions were enhanced to produce better coverage. In addition, the assertions should also be created with as uniform structure as possible to ease assertion generator script development in the future. To achieve these targets, the manually created assertions were integrated into the assertions created by the formal verification tool. By doing this, the whole relevant functionality of SW interfaces was covered. However, the structure of the assertions was not as uniform as was desired. In this thesis, a new verification method for SoC module SW interface was produced. The developed method at its current state cannot replace the simulation-based methods, however, because the assertions are not generated automatically. Nevertheless, the method was suggested to be considered as an additional way to verify SW interfaces.